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pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 1 ? www.pericom.com ????? features ? real time aeq 4-channel video/audio decoder for wd1(960h) and d1 cameras ? built-in adaptive equalizer(aeq) for the best picture image in the several hundred meter coax cable condition ? proprietary pericom aeq technology recover weak, noisy, or unstable analog input signals ? resilient sync tip detection to lock video signal in a noisy environment ? programmable sharpness, cti, hue, saturation, contrast and brightness ? support time multiplexed format of itu-r bt.656 output with 54/108mhz or72/144mhz ? provides a programmable mapping from four or eight (non-real-time) analog video inputs to four bt.656 digital outputs ? ntsc(m), ntsc 4.43, pal (b, d, g, h, i, m, nc, 60) standard support ? high performance 5h comb filter for all ntsc/pal standards ? built-in 10-bit audio codec to allow 5analog audio inputs and 1 audio output ? mixed audio analog output for multiple audio channels ? two serial audio formats (i2s and dsp) are supported for recording/mixing output and playback input ? selectable master and slave serial audio interface ? multiple audio sample rates for 8, 16, 32, 44.1, 48khz audio frequency ? integrated video pll for 108mhz,144mhz clock output ? two-wire serial interface(i 2 c) for register access ? provide system interrupt request for video ? packages: 128-pin lqfp description pi7vd9004abh is aeq 4-channel video decoders and audio codec. built-in adaptive equalizer (aeq)recover the noisy signals caused by long or small wire gauge coax cables and display the best picture image view quality. the video decoder converts ntsc, pal analog composite video broadcasting signal (cvbs) into digital components ycbcr for video controller or processor to perform pre-view, compression and storage etc. the converted digital video streams complying with itu-r bt.656 are transported in time multiplexed format, which contains one, two or four video channels. single 27mhz reference crystal clock support ntsc, pal and 960h standard resolution. each video channel contains 10-bit adc, proprietary clamp, automatic gain controller and 5h comb filter for separating luminance & chrominance to reduce artificial noise. application ? video security dvrs, pc-dvr, video capture cards ? automotive camera driver assistant systems ? video broadcasting equipment pi7vd9004abh 4 \ ch ? aeq video ? decoder h.264 ? video ? soc cameras vid eo/audio ? signals itu \ r ? bt.656 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 2 ? www.pericom.com ????? ? table of contents 1 ? pi7vd9004abh block diagram .................................................................................................... ......................................... 6 ? 2 ? pin configuration(128-lqfp) ................................................................................................... .............................................. 7 ? 3 ? pin-out information ........................................................................................................... ....................................................... 9 ? 4 ? functional description ........................................................................................................ ................................................... 11 ? 4.1 ? video/audio analog input ...................................................................................................... .............................................. 11 ? 4.2 ? clamping and automatic gain control ........................................................................................... .................................... 11 ? 4.3 ? video decoder ................................................................................................................. ........................................................ 11 ? 4.4 ? adaptive equalization ......................................................................................................... .................................................... 11 ? 4.5 ? comb filter and y/c separation ................................................................................................ ............................................ 12 ? 4.6 ? video signal processing ....................................................................................................... ................................................... 12 ? 4.7 ? video output port ............................................................................................................. ...................................................... 13 ? 4.8 ? analog audio input ............................................................................................................ ......................................... 14 ? 4.9 ? audio processing .............................................................................................................. ............................................. 14 ? 4.10 ? pi7vd9004abh cascade mode ..................................................................................................... ................................. 17 ? 4.11 ? i 2 c host interface .............................................................................................................. ................................................. 19 ? 5 ? configuration, control, and status register map ............................................................................... ............................... 20 ? 6 ? control register .............................................................................................................. ......................................................... 21 ? 6.1 ? registers ..................................................................................................................... ......................................................... 21 ? 6.1.1 ? video status register C offset 00h/10h/20h/30h (default: 00h) ..................................................... 21 ? 6.1.2 ? brightness control register C offs et 01h/11h/21h/31h(default=00h) .................................... 22 ? 6.1.3 ? contrastcontrol register C offset 02h/12h/22h/32h(default=64h) ........................................ 22 ? 6.1.4 ? sharpness control register C offset 03h/13h/23h/33h(default=00h) ...................................... 22 ? 6.1.5 ? chroma(u) gain register C offset 04h/14h/24h/34h(default=80h) .............................................. 22 ? 6.1.6 ? chroma(v) gain register C offset 05h/15h/25h/35h(default=80h) .............................................. 23 ? 6.1.7 ? huecontrol register C offset 06h/16h/26h/36h(default=00h) ...................................................... 23 ? 6.1.8 ? reserved registerC o ffset07h/17h/27h/37h ..................................................................................... .... 23 ? 6.1.9 ? reserved register C o ffset 08h/18h/28h/38h .................................................................................... .... 23 ? 6.1.10 ? reserved register C o ffset09h/19h/29h/39h ..................................................................................... .... 23 ? 6.1.11 ? reserved register C o ffset 0ah/1ah/2ah/3ah .................................................................................... . 23 ? 6.1.12 ? reserved register C offset 0bh/1bh/2bh/3bh .................................................................................... .. 23 ? 6.1.13 ? reserved register C offset 0ch/1ch/2ch/3ch .................................................................................... . 23 ? 6.1.14 ? reserved register C o ffset 0dh/1dh/2dh/3dh .................................................................................... 23 ? 6.1.15 ? standard selection register C offset 0eh/1eh/2eh/3eh(default=77h) .................................. 23 ? 6.1.16 ? reservedregister C offs et 0fh/1fh/2fh/3fh ..................................................................................... ... 23 ? 6.1.17 ? reserved register C offset 40h-50h ............................................................................................ .............. 23 ? 6.1.18 ? fbitinv register C offs et 51h(default=00h) .................................................................................... ......... 23 ? 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 3 ? www.pericom.com ????? ? 6.1.19 ? reserved register C offset 52h-56h ............................................................................................ .............. 24 ? 6.1.20 ? hblen register C offset 57h/ 58h/59h/5ah(default=90h) .................................................................... 24 ? 6.1.21 ? reserved register C offset 5bh ................................................................................................ ................... 24 ? 6.1.22 ? bgctl-register C offset 5ch(default=00h) ...................................................................................... ......... 24 ? 6.1.23 ? reserved register C offset 5dh-5fh ............................................................................................ ............. 24 ? 6.1.24 ? reserved register C offset 60h ................................................................................................ ................... 24 ? 6.1.25 ? crystal clock select register C offset 61h(default=03h) ............................................................ 24 ? 6.1.26 ? 36m/gpio_oe register C o ffset 62h(default=00h) ................................................................................ ... 24 ? 6.1.27 ? channel id01 register C offset 63h(default=10h) ............................................................................... . 25 ? 6.1.28 ? channel id23 register C offset 64h(default=32h) ............................................................................... . 25 ? 6.1.29 ? pixel output bus tri-state control regi ster C offset 65h(default=00h) ........................... 25 ? 6.1.30 ? reserved register C offset 66-6fh ............................................................................................. ................ 26 ? 6.1.31 ? audio clock control register C offset 70h(default=08h) ........................................................... 26 ? 6.1.32 ? i2s audio input control register C offset 71h(default=00h) ...................................................... 26 ? 6.1.33 ? reserved register C offset72h-7ah ............................................................................................. ............. 26 ? 6.1.34 ? sdout_m select (r) register C offset 7bh(default=00h) ................................................................... 26 ? 6.1.35 ? sdout_m select (l) register C offset 7ch(default=00h) ................................................................... 27 ? 6.1.36 ? extended line select register C offset 7dh(default=e4h) ............................................................ 27 ? 6.1.37 ? sdout_m registerC offset 7eh(default=00h) .................................................................................... ..... 28 ? 6.1.38 ? mix ratio value for line_in4 register C offset 7fh(default=08h) ............................................ 28 ? 6.1.39 ? software reset registerC offset 80h(default=00h) ........................................................................... 29 ? 6.1.40 ? reserved register C offset 81h-84h ............................................................................................ .............. 29 ? 6.1.41 ? video source selection register C offset 85h (default=00h) ...................................................... 29 ? 6.1.42 ? reserved register C offset 86h-88h ............................................................................................ .............. 29 ? 6.1.43 ? audio fs mode registerC offset 89h(default=00h) .............................................................................. 29 ? 6.1.44 ? reserved register C offset 8ah-9eh ............................................................................................ ............. 30 ? 6.1.45 ? pixclk 0 delay registerC offset 9fh(default=00h) .............................................................................. 30 ? 6.1.46 ? reserved register C offset a0h-b0h ............................................................................................ ............. 30 ? 6.1.47 ? ch8iden register C offset b1h(default=00h) .................................................................................... ....... 30 ? 6.1.48 ? reserved register C offset b2h-c7h ............................................................................................ ............. 30 ? 6.1.49 ? gpio_0_1 mode registerC offset c8h(default=00h) .............................................................................. 30 ? 6.1.50 ? gpio_2_3 mode registerC offset c9h(default=00h) .............................................................................. 31 ? 6.1.51 ? video output mode register C offset cah(default=00h) ............................................................... 31 ? 6.1.52 ? gpio polarity register C offset cbh (default=00h) ............................................................................ 32 ? 6.1.53 ? pixout output ch2 select register C offset cch (default=39h) ................................................ 32 ? 6.1.54 ? pixout output ch1 select register C offset cdh (default=e4h) ............................................... 32 ? 6.1.55 ? reserved registerC offset ceh ................................................................................................. .................. 33 ? 6.1.56 ? serial mode control register C offset cfh(default=00h) ............................................................. 33 ? 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 4 ? www.pericom.com ????? ? 6.1.57 ? reserved registerC offset d0h-d1h ............................................................................................. ............ 33 ? 6.1.58 ? sdout_rm output registerC offset d2h(default=03h) .................................................................... 33 ? 6.1.59 ? sdout_r_seq_1_0 registerC o ffset d3h(default=10h) ........................................................................ 34 ? 6.1.60 ? sdout_r_seq_3_2 registerC o ffset d4h(default=32h) ........................................................................ 34 ? 6.1.61 ? sdout_r_seq_5_4 registerC o ffset d5h(default=54h) ........................................................................ 35 ? 6.1.62 ? sdout_r_seq_7_6registerC offsetd6h(default=76h) .......................................................................... 36 ? 6.1.63 ? sdout_r_seq_9_8 registerC o ffset d7h(default=98h) ........................................................................ 37 ? 6.1.64 ? sdout_r_seq_b_a registerC offs et d8h(default= bah) .................................................................... 37 ? 6.1.65 ? sdout_r_seq_d_c registerC offs et d9h(default= dch) ................................................................... 38 ? 6.1.66 ? sdout_r_seq_f_e registerC offs et dah(default= feh) ..................................................................... 39 ? 6.1.67 ? i2s master control registerC offset dbh(default= c2h) ............................................................... 40 ? 6.1.68 ? mix_mute registerC offset dch(default=00h) ................................................................................... ... 40 ? 6.1.69 ? mix ratio value for line_in0 & line_in1 register C offset ddh (default=88h) ................. 40 ? 6.1.70 ? mix ratio value for line_in2 & line_in3 register C offset deh (default=88h) .................. 41 ? 6.1.71 ? pb ratio register C offset dfh (default=08h) .................................................................................. ....... 41 ? 6.1.72 ? mixing output control registerC offset e0h(default=14h) ....................................................... 42 ? 6.1.73 ? reserved registerC offset e1h-f8h ............................................................................................. .............. 42 ? 6.1.74 ? pixclk output mode registerC offset f9h (default=00h) ............................................................... 42 ? 6.1.75 ? ccir656 control registerC o ffset fah(default=00h) ........................................................................ 43 ? 6.1.76 ? clock polarity registerC offset fbh(default=0fh) .......................................................................... 43 ? 6.1.77 ? video/audio detection en able registerCoffset fch (default=ffh) ...................................... 44 ? 6.1.78 ? video/audio detection status regi sterCoffset fdh (default=00h) ...................................... 44 ? 6.1.79 ? device id_h registerC o ffset feh(default=00h) ................................................................................. ... 44 ? 6.1.80 ? device id - l registerC offset ffh(default=e8h) ............................................................................... .... 45 ? 7 ? electrical characteristics .................................................................................................... ..................................................... 45 ? 7.1 ? absolute maximum ratings....................................................................................................... ............................................ 45 ? 7.2 ? operating conditions .......................................................................................................... ................................................... 45 ? 7.3 ? dc electrical characteristics ................................................................................................. ................................................ 45 ? 7.3.1 ? power dissipation ............................................................................................................. ............................................ 46 ? 7.3.2 ? power-on sequence of 3.3v and 1.0v power ...................................................................................... ..................... 46 ? 7.3.3 ? crystal specifications ........................................................................................................ ............................................ 46 ? 7.4 ? ac electrical characteristics ................................................................................................. ................................................. 46 ? 7.4.1 ? audio electrical characteristics .............................................................................................. .................................... 47 ? 7.4.2 ? pixel clock and video data timing ............................................................................................. .............................. 47 ? 7.4.3 ? audio interface timing ........................................................................................................ ........................................ 49 ? 7.4.5 ? i2c host port timing .......................................................................................................... ......................................... 50 ? 8 ? packaging mechanical .......................................................................................................... ................................................... 51 ? 9 ? ordering information .......................................................................................................... ................................................... 52 ? 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 5 ? www.pericom.com ????? ? 10 ? related product information ................................................................................................... .............................................. 52 ? 11 ? reference document information ................................................................................................ ........................................ 52 ? 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 6 ? www.pericom.com ????? ? 1 pi7vd9004abh block diagram video input sources: cv_ina0, cv_inb0, cv_ina1, cv_inb1, cv_ina2, cv_inb2, cv_ina3 and cv_inb3 bt.656 tdm ports: pixout_0, pixout_1, pixout_2 and pixout_3 audio input sources: line_in0, line_in1, line_in2, line_in3, and line_in4 i2s/dsp audio interface (sclk_r, lrck_r, sdout_r and sdout_m), (sclk_p, lrck_p and sdin_p), (sd_linki, sd_linko) 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 7 ? www.pericom.com ????? ? 2 pin configuration(128-lqfp) 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 8 ? www.pericom.com ????? ? pin name pin name pin name pin name 1 vss 33 pixout_2[4] 65 pixout_0[5] 97 adac_vdd 2 vss 34 vss 66 pixout_0[4] 98 adac_vdd 3 vss 35 vddc 67 vss 99 line_out 4 vddc 36 pixout_2[3] 68 pixout_0[3] 100 vss 5 tm1 37 pixout_2[2] 69 pixout_0[2] 101 vss 6 sa0 38 pixout_2[1] 70 pixout_0[1] 102 vcm 7 sa1 39 pixout_2[0] 71 pixout_0[0] 103 line_in0 8 vss 40 vss 72 vd33 104 line_in1 9 vddc 41 vd33 73 sclk_ r 105 line_in2 10 reset_l 42 pixclk_po 74 lrck_ r 106 line_in3 11 scl 43 pixclk_no 75 sdout_ r 107 line_in4 12 sda 44 vss 76 sdout_m 108 adc_vdd 13 vss 45 vddc 77 vss 109 adc_vdd 14 sd_linki 46 xin 78 sclk_p 110 cv_ina0 15 vd33 47 xout 79 lrck_p 111 cv_inb0 16 pixout_3[7] 48 vss 80 sdin_p 112 vss 17 pixout_3[6] 49 vd33 81 sd_linko 113 cv_ina1 18 pixout_3[5] 50 pixout_1[7] 82 vd33 114 cv_inb1 19 pixout_3[4] 51 pixout_1[6] 83 gpio_0 115 adc_vdd 20 vss 52 pixout_1[5] 84 gpio_1 116 cv_ina2 21 vddc 53 pixout_1[4] 85 gpio_2 117 cv_inb2 22 pixout_3[3] 54 vss 86 gpio_3 118 vss 23 pixout_3[2] 55 vddc 87 vddc 119 cv_ina3 24 pixout_3[1] 56 pixout_1[3] 88 int 120 cv_inb3 25 pixout_3[0] 57 pixout_1[2] 89 vss 121 adc_vdd 26 vss 58 pixout_1[1] 90 vss 122 adc_vdd 27 vddc 59 pixout_1[0] 91 nc 123 vss 28 vss 60 vd33 92 nc 124 adc_vdd 29 vd33 61 vss 93 nc 125 vss 30 pixout_2[7] 62 vddc 94 nc 126 adc_vdd 31 pixout_2[6] 63 pixout_0[7] 95 nc 127 vddpll 32 pixout_2[5] 64 pixout_0[6] 96 nc 128 vddpll 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 9 ? www.pericom.com ????? ? 3 pin-out information analog video/audio interface pin name pin number t yp edescri p tion cv_ina0, cv_inb0, cv_ina1, cv_inb1, cv_ina2, cv_inb2, cv_ina3, cv_inb3 110, 111, 113, 114, 116, 117, 119, 120 analog cvbs input a of video channel 0 cvbs input b of video channel 0 cvbs input a of video channel 1 cvbs input b of video channel 1 cvbs input a of video channel 2 cvbs input b of video channel 2 cvbs input a of video channel 3 cvbs in p ut b of video channel 3 vcm 102 analo g connect to an external ca p acitor line_in0, line_in1, line_in2, line_in3, line_in4 103, 104, 105, 106, 107 analog line input of audio channel 0 line input of audio channel 1 line input of audio channel 2 line input of audio channel 3 line input of audio channel 4 line_out 99 analog mixed analog audio output digital video/audio interface pin name pin number t yp edescri p tion pixout_0[7:0] 63, 64, 65, 66,68,69, 70,71 output bt.656 time multiplex division output of port 0 pixout_1[7:0] 50, 51, 52, 53, 56,57,58,59 output bt.656 time multiplex division output of port 1 pixout_2[7:0] 30, 31, 32, 33, 36, 37, 38, 39 output bt.656 time multiplex division output of port 2 pixout_3[7:0] 16, 17, 18, 19, 22, 23, 24, 25 output bt.656 time multiplex division output of port 3 gpio_0 83 output according to register setting, it outputs gpo, hsyc, vsync, fdflag, active and vdloss of channel 0 gpio_1 84 output according to register setting, it outputs gpo, hsyc, vsync, fdflag, active and vdloss of channel 1 gpio_2 85 output according to register setting, it outputs gpo, hsyc, vsync, fdflag, active and vdloss of channel 2 gpio_3 86 output according to register setting, it outputs gpo, hsyc, vsync, fdflag, active and vdloss of channel 3 sclk_r 73 input/ out p ut record audio serial clock. it is an input pin under slave mode, while out p ut p in under master mode. lrck_ r 74 input/ out p ut record audio serial sync pulse. it is an input pin under slave mode, while out p ut p in under master mode. sdout_ r 75 out p ut record audio serial data out p ut. sdout_m 76 out p ut mixin g audio serial data out p ut. sclk_p 78 input/ out p ut playback audio serial clock. it is an input pin under slave mode, while out p ut p in under master mode 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 10? www.pericom.com ????? ? lrck_p 79 input/ out p ut playback audio serial sync pulse. it is an input pin under slave mode, while out p ut p in under master mode. sdin_p 80 in p ut pla y back audio serial data in p ut. sd_linki 14 in p ut chi p -to-chi p audio serial data in p ut. sd_linko 81 out p ut chi p -to-chi p audio serial data out p ut. system control interface pin name pin number t yp edescri p tion reset_l 10 in p ut chi p reset. active low. xin 46 input 27mhz or 54mhz crystal input or 27mhz/54mhz/108mhz oscillator in p ut xout 47 out p ut 27mhz or 54mhz cr y stal out p ut pixclk_p0 42 output positive output cloc k signal running at 27/54/108mhz (720h mode) or 36/72/144mhz (960h mode) for bus pixout_0. pixclk_n0 43 output negative output clock signal running at 27/54/108mhz (720h mode) or 36/72/144mhz (960h mode) for bus pixout_0 tm1 5 in p ut test p in. tied to vss. sa1 7 in p ut device address 1 of i2c slave interface sa0 6 in p ut device address 0 of i2c slave interface scl 11 in p ut in p ut clock si g nal of i2c slave interface sda 12 input/ out p ut data signal of i2c slave interface int 88 out p ut interru p t si g nal to s y stem. active hi g h. power and ground pin name pin number t yp edescri p tion vddc 4, 9, 21, 27, 35, 45, 55, 62, 87 power 1.0v power for core logic vd33 15, 29, 41, 49, 60, 72, 82 power 3.3v power for io pads vss 1, 2, 3, 13, 20, 26, 28, 34, 40, 44, 48, 54, 61, 67, 77, 89, 90, 100, 101, 112, 118, 123, 125 ground ground for video adc, audi o adc, audio dac, pll, core logic and io pads adc_vdd 108, 109, 115, 121, 122, 124, 126 power 3.3v power for video adc and audio adc. adac_vdd 97, 98 power 3.3v power for audio dac vddpll 127, 128 power 3.3v power for av pll no connection pins pin name pin t yp edescri p tion nc 91, 92, 93, 94, 95, 96 n/a not connected pin. please let these p ins floatin g . 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 11? www.pericom.com ????? ? 4 functional description 4.1 video/audio analog input pi7vd9004abh offers4 channels ntsc, pal (720h or 960h) fo rmat composite (cvbs) inputs(cv_inax and cv_inbx, x= 0,1,2,3). when the input signal is weak and the color burst is not able to be recognized, the video is automatically switched to black and white mode to enhance the picture image quality. format lines field fsc country ntsc-m 525 60 3.579545 mhz u.s., many others ntsc-japan 525 60 3.579545 mhz japan * ntsc (4.43) 525 60 4.433619 mhz transcoding pal-b, g, n 625 50 4.433619 mhz many pal-i /h /d 625 50 4.433619 mhz belgium ,china great britain, others pal-m 525 60 3.575612 mhz brazil pal-cn 625 50 3.582056 mhz argentina pal-60 525 60 4.433619 mhz china * ntsc-japan has 0 ire setup 4.2 clamping and automatic gain control each analog input channel has built-in clamping circuits to restore signal dc level. automatic gain control (agc) circuits in the internal video processor can compensate average input video signal level for each analog input channel. the agc and clamping circuits prevent signal level saturation and allow the video decoder to deliver the best signal-to-noise performance. on the other hand, the agc cooperates with the digital multiplier of video dec oder to boost the weak signals. the circuits perform automatic gain control through in ternal feedback look. manual gain control is also available through configuring the video decoder control and status registers 4.3 video decoder the video decoder in the chip converts ntsc and pal video signals to 8-bit itu-r bt.656 format. the chip includes four high speed and low power 10-bit analog-to-digital converters (adc) with 2x sampling rate to support 4-channel video decoding. when the incoming video is in the 720h format, the sampling rate is 27mhz or 54mhz by 2x factor. for 960h format, the sampling rate is 36mhz or 72mhz by 2x factor. the chip implements proprieta ry circuit design that is optimized for locking in weak, noisy, or unstable signals. the minimal signal voltage that can be locked in is at 160/80 mv 4.4 adaptive equalization the cvbs is suffered from channel loss by an extended transmission distance (greater th an 500m) and a small diameter (less than 0.5mm) of cctv cable. the distortion on cvbs after the energy reduction effect of cable length is illustrated as below. for example, a multi-burst test signal is respectively me asured at 0.5m and 500m of cable.it appears that color burst and sync tip have sever degration after 500m transmission distance. adaptive equalization on the distorted cvbs recovers the signal back to close to the original level. since the diff erent cable conditions present var ious effects on cvbs picture image, the adaptive equalization provides to compensate th e signal loss on some frequency components pertinent to the coax cable. 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 12? www.pericom.com ????? ? ? ? 4.5 comb filter and y/c separation thevideo decoder is capable of separating luma (y) and chroma (c) of nts c or pal video signals using 5-line adaptive comb filter or notch/band-pass filter. the comb filter searches for correlation between 5 lines of input video stored in the internal buffer. the lines are averaged based on the degree of correlation to produce the output video line. if no correlation is found between the 5 lines of video, notch/band-pass filter is used. this process is very e ffective at reducing cross-luma and cross-chroma noise. the noise appears as artifacts that de grade the image quality. reduction of the noise improves the image quality significantly. 4.6 video signal processing the chip is capable of processing digital video signal to fu lfill better detection in a noisy environment and achieve good image quality for viewing as well. for video signal detection, a resilient sync tip detection mechanism is implemented to locate vsync and hsync correctly in order to lock the video frame or video line. 6.392 6.394 6.396 6.398 6.4 6.402 6.404 6.406 6.408 6.41 6.412 x 10 5 -100 0 100 200 300 400 500 600 0.5m multi-burst test signal 1.4878 1.488 1.4882 1.4884 1.4886 1.4888 1.489 1.4892 1.4894 1.4896 x 10 6 -100 0 100 200 300 400 500 600 700 500m multi-burst test signal 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 13? www.pericom.com ????? ? in general, the poor power adaptor or camera would introduce high frequency ripples coupling with sync tip to cause the misjudgment on the beginning of a video frame or line. the built-in video processing circuit is able to decouple the noise from sync tip to prevent from video loss. a sharpness filter is implemented to offer programmable 16 level gains to increase the high frequency and edge information of luma for better viewing on the contour of ea ch object. through the i2c serial interface, hue, contrast, brightness and saturation can be programmed in the configur ation registers. hue can be controlled in 256 steps from -180 degrees to +180 degrees. saturation can be programmed in 256 grades. brightness can be adjusted in 256 levels. 4.7 video output port the four cvbs analog video channels are converted into four individual digital video data streams. there are four video output ports (pixout_0, pixout_1, pixo ut_2 and pixout_3) in the chip and each video output port can carry several converted digital video data stream following itu-r bt.656 compatible data format. the video data of each port is synchronous with the corresponding clock signals of pixclk _po or pixclk_no. the freq uency of pixclk_*o can be operated at 1x, 2x or 4x of 27mhz (720h mode) or 36mhz (960h mode). when the clock freque ncy is 2x or 4x rate, the video port outputs 2-channel or 4-channel video data s tream in time-multiplexed fo rmat. the clock phase of pixclk_poor pixclk_nocan be progra mmed by delay cells through writing delay value into the registers of pixclk_p_del or pixclk_n_del. also, the clock polarity can be controlled through inverter by setting or resetting the register of pixclk_p_pol or pixclk_n_pol. the flexibility on changing clock phase or polarity facilitates the timing design for video data stream on pcb. figure 4-1time-multiplexed format with 108/144mhz 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 14? www.pericom.com ????? ? 4.8 analog audio input the audio adc offers 5 channels of analog inputs (line_inx, x= 0, 1, 2, 3, 4) with a peak-to-peak voltage range from 0.5v to 2v. each input channel contains 4-bit programmable gain amplifier and an adc with maximum over-sampling speed of 3.6m sample/s. a pseudo differential input is used to minimi ze board level noise problems. the converted audio data stream is fed into a low pass filter to decimate audio sample at an appropriate audio sampling rate such as 8 khz, 16 khz, 32 khz, 44.1 khz and 48 khz etc. 4.9 audio processing the audio processor accepts 5 digital audio streams from audio adc. it also receives 2 additional digital serial audio data from pins. one digital serial audio data is sdin_p coming from av compression processor, while the other one is sd_linki coming from companion device. sdin_p represents the decompressed audio data for playback pu rpose. sd_linki is used to cascade with as many as 12 or 15 digital audio outputs from th ree other pi7vd9004abh chips for forming one timing multiplexed i2s digital serial audio data containing 16 or 20 digital audio channels. this device processes these 5 digital audio streams and 2 digital serial audio data, then generates one mixing analog audio signal and three di gital serial audio data to fulf ill the functions of mixing, recording and cascading etc. for audio mixing, this device has both analog and digital form at. the built-in mixer selects among all audio input data to generate the mixing digital audio data (sdout_m), which conne cts to audio dac for converting to mixing analog audio signal output (line_out). for audio recording, the audio processor performs multiplexing over 12 or 15 digital audio streams in timing division way to generate record digital audio output data (sdout_r). fo r the digital serial audio data sdout_r and sdout_m, they are both synchronized with sclk_r and lrck_r. as to sd in_p, it is synchronized with sclk_p and lrck_p. these digital serial audio data support two formats of i2s and dsp that can be selected by control bits rm_sync in the register at offset 0xd2 and pb_sync in the register at offset 0xdb. meanwhile, the record and playback digital serial audio interfaces of pi7vd9004a(a/b/c)h can be acted as master or slave mode based upon the setting of aclkrmaster and pb_master bits in the register at offset 0xdb figure 4-2time-multiplexed format with 54/72mhz 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 15? www.pericom.com ????? ? this device supports audio system cloc k with 256fs or 320fs mode, which is controlled by ain5md register. the record output pin contains several channel inputs that can be defi ned by the registers at offset of 0xd2~ 0xda describing the number and sequence of recorded audio streams. it supports 8bit and 16bit record data width for trading off between higher audio qualities and saving disk storage space. by contro lling bit2 of register at offset 0xdb, the chip allows to select the output record data width to be either 8-bit or 16-bit mode. figure 4-3 audio processing block 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 16? www.pericom.com ????? ? 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 17? www.pericom.com ????? ? 4.10 pi7vd9004abh cascade mode for audio cascading, the chip redirects sdout_r as sd_lin ko to connect with sd_linki of another pi7vd9004ab product, which cascades its original sd out_r and sd_linki to create a new sdout_r. pi7vd9004ab can support 16 channel data output on first level chip record output pin for saving pin layout on pcb board. the cascade chips have to use same crystal clock source and same reset signal. figure 4-4 playback input format 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 18? www.pericom.com ????? ? figure 4-5 audio cascading example 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 19? www.pericom.com ????? ? 4.11 i 2 c host interface the processor can access the internal register by executing read or write command to the indexed locations to implement the function of detecting audio and video signal and reveals the detection status through the configuration registers. if any audio or video channel is present or absent, interrupt pin (i nt) can notify the status to the processor to manage cpu resource effectively by polling the status. the chip supports flexibilities to select various detection modes and enable individual audio/video channel for generating interrupt. these control bits to interrupt pin are defined in the registers of avdet_mode, avdet1_ena, avdet2_ena, a51det_ena and a52det_ena. ? figure 4-6 interrupt timing diagram of audio/video detection 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 20? www.pericom.com ????? ? 5 configuration, control, an d status register map address function 00h/10h/20h/30h (00h) video status 01h/11h/21h/31h (00h) bri g htness control 02h/12h/22h/32h (64h) contrast control 03h/13h/23h/33h (00h) shar p ness control 04h/14h/24h/34h (80h) chroma (u) gain 05h/15h/25h/35h (80h) chroma (v) gain 06h/16h/26h/36h (00h) hue control 07h/17h/27h/37h reserved 08h/18h/28h/38h reserved 09h/19h/29h/39h reserved 0ah/1ah/2ah/3ah reserved 0bh/1bh/2bh/3bh reserved 0ch/1ch/2ch/3ch reserved 0dh/1dh/2dh/3dh reserved 0eh/1eh/2eh/3eh (77h) standard selection 0fh/1fh/2fh/3fh reserved 40h-50h reserved 51h (00h) f-bit of sav/eav inverted 52h-56h reserved 57h/58h/59h/5ah (90h) blankin g len g th of horizontal line 5bh reserved 5ch (00h) video fast switch 5dh-60h reserved 61h (03h) crystal clock select 62h (00h) 36m & gpio output enable 63h (10h) id for video channel 0 & 1 64h (32h) id for video channel 2&3 65h (00h) clock out p ut control 66h-6fh reserved 70h (08h) audio clock control 71h (00h) i2s audio input control 72h-7ah reserved 7bh (00h) sdout_m select (r) 7ch (00h) sdout_m select (l) 7dh (e4h) extended line select 7eh reserved 7fh (08h) mix ratio 4 80h (00h) software reset 81h-84h reserved 85h (00h) video source selection 86h-88h reserved 89h (00h) audio fs mode 8ah-9eh reserved 9fh (00h) pixclk 0dela y a0h-b0h reserved b1h (00h) channel id for 8 video sources b2h-c7h reserved c8h (00h) gpio_0_1 mode 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 21? www.pericom.com ????? ? address function c9h (00h) gpio_2_3 mode cah (55h) video out p ut mode cbh (00h) gpio polarit y cch (e4h) pixout out p ut ch2 select cdh (00h) pixout out p ut ch1 select ceh reserved cfh (00h) serial mode control d0h-d1h reserved d2h (03h) sdout_rm out p ut d3h (10h) sdout_r_seq_1_0 d4h(32h) sdout_r_seq_3_2 d5h (54h) sdout_r_seq_5_4 d6h (76h) sdout_r_seq_7_6 d7h (98h) sdout_r_seq_9_8 d8h (bah) sdout_r_seq_b_a d9h (dch) sdout_r_seq_d_c dah (feh) sdout_r_seq_f_e dbh (c2h) i2s master control dch reserved ddh (88h) mix ratio 0 & 1 deh (88h) mix ratio 2 & 3 dfh (08h) pb ratio e0h (14h) mixin g out p ut control e1h (00h) audio detect threshold 1 e2h (88h) audio detect threshold 2 e3h (88h) audio detect threshold 3 e4h-f8h reserved f9h (00h) pixclk out p ut mode fah (00h) ccir656 control fbh (0fh) clock polarit y fch (ffh) av detection enable fdh (00h) av detection status feh (00h) device id_h ffh (c8h) device id_l 6 control register 6.1 registers re g ister t y pe descriptions r read onl y rw read/write 6.1.1 video status register C offset 00h/10h/20h/30h (default: 00h) bit function type description 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 22? www.pericom.com ????? ? bit function type description 0 det50 r 0: 60hz source detected 1: 50hz source detected 1 mono r 0:color burst signal detected 1: no color burst si g nal detected 2 reserved r reset to 0b 3 vloc k r 0: vertical logic is not locked 1: vertical lo g ic is locked to incomin g video 4 reserved r reset to 0b 5 sloc k r 0: sub-carrier sync is not detected 1: sub-carrier s y nc is detected 6 hloc k r 0:horizontal sync is not detected 1: horizontal s y nc is detected 7 vdloss r 0: video is detected 1: video not p resent 6.1.2 brightness control register C offset 01h/11h/21h/31h(default=00h) bit function type description [7:0] brightness rw these signed bits control the brightness.value range from -128 to 127 8'h7f: bri g htest; 8'h80: darkest ;8h00 : no effect 6.1.3 contrastcontrol register C offs et 02h/12h/22h/32h(default=64h) bit function type description [7:0] contrast rw these unsigned bits control the luminance gain. 8'h7f: maximum contrast 8'h00: minimum contrast 6.1.4 sharpness control register C offset 03h/13h/23h/33h(default=00h) bit function type description [3:0] sharpness rw these bits control the amount of sharpness enhancement on the luminance signals "0" has no effect on the output image "1" through "15" provides sharpness enhancement with "15" bein g the stron g est [7:4] reserved r reset to 0h 6.1.5 chroma(u) gain register C offs et 04h/14h/24h/34h(default=80h) bit function type description [7:0] chroma (u) gain rw chroma g ain value of controllin g the color saturation 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 23? www.pericom.com ????? ? 6.1.6 chroma(v) gain register C offs et 05h/15h/25h/35h(default=80h) bit function type description [7:0] chroma (v) gain rw chroma g ain value of controllin g the color saturation 6.1.7 huecontrol register C offset 06h/16h/26h/36h(default=00h) bit function type description [7:0] hue rw these signed bits control color hue. +90c(7fh) to -90c(80h) 6.1.8 reserved registerC offset07h/17h/27h/37h 6.1.9 reserved register C offset 08h/18h/28h/38h 6.1.10 reserved register C offset09h/19h/29h/39h 6.1.11 reserved register C offset 0ah/1ah/2ah/3ah 6.1.12 reserved register C offset 0bh/1bh/2bh/3bh 6.1.13 reserved register C offset 0ch/1ch/2ch/3ch 6.1.14 reserved register C offset 0dh/1dh/2dh/3dh 6.1.15 standard selection register C offset 0eh/1eh/2eh/3eh(default=77h) bit function type description [2:0] standard selection rw 0: ntsc(m) 1: pal(b,d,g,h,i) 2:not valid 3: ntsc4.43 4: pal(m) 5: pal(cn) 6: pal60 7: auto detection [3] reserved r reset to 0b [6:4] current standard detected r 0: ntsc(m) 1: pal(b,d,g,h,i) 2:not valid 3: ntsc4.43 4: pal(m) 5: pal(cn) 6: pal60 7:not valid [7] reserved r reset to 0b 6.1.16 reservedregister C offset 0fh/1fh/2fh/3fh 6.1.17 reserved register C offset 40h-50h 6.1.18 fbitinv register C offset 51h(default=00h) bit function type description [0] fbitinv0 r/w 0: f-bit in the 4 th byte of 656 eav/sav for channel 1 is not inverted. 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 24? www.pericom.com ????? ? bit function type description 1: f-bit in the 4 th b y te for channel 0 is inverted. [1] fbitinv1 r/w 0: f-bit in the 4 th byte of 656 eav/sav for channel 2 is not inverted. 1: f-bit in the 4 th b y te for channel 1is inverted. [2] fbitinv2 r/w 0: f-bit in the 4 th byte of 656 eav/sav for channel 3 is not inverted. 1: f-bit in the 4 th b y te for channel 2is inverted. [3] fbitinv3 r /w 0: f-bit in the 4 th byte of 656 eav/sav for channel 4 is not inverted. 1: f-bit in the 4 th b y te for channel 3is inverted. [7:4] reserved r reset to 0b 6.1.19 reserved register C offset 52h-56h 6.1.20 hblen register C offset 57h/58h/59h/5ah(default=90h) bit function type description [7:0] hblenn[7:0] n=1,2,3,4 r display the blanking length starting from eav to sav code. (1) in 27mhz d1 mode: 90h for pal while 8ah for ntsc (2) in 36mhz wd1 mode: c0h for pal while b8h for ntsc 6.1.21 reserved register C offset 5bh 6.1.22 bgctl-register C offset 5ch(default=00h) bit function type description [3:0] reser v ed r w reset to 0h [4] reserved r reset to 0h [5] reserved r reset to 0b [7:6] reserved r reset to 0b 6.1.23 reserved register C offset 5dh-5fh 6.1.24 reserved register C offset 60h 6.1.25 crystal clock select register C offset 61h(default=03h) bit function type description [1:0] xinmd rw xin input frequency 0:27mhz 1:54mhz 2:108mhz 3: 54/27mhz [7:2] reserved r w reset to 00h 6.1.26 36m/gpio_oe register C offset 62h(default=00h) bit function type description 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 25? www.pericom.com ????? ? bit function type description [0] gpio_0oe rw 0: gpio_0 pin is input. 1: gpio_0 p in is out p ut. [1] gpio_1oe rw 0: gpio_1 pin is input. 1: gpio_1 p in is out p ut. [2] gpio_2oe r w 0: gpio_2 pin is input. 1: gpio_2 p in is out p ut. [3] gpio_3oe r w 0: gpio_3 pin is input. 1: gpio_3 p in is out p ut. [4] o36m0 r w 0: channel 0 generates 27mhz video dat a 1: channel 0 g enerates 36mhz video dat a [5] o36m1 r w 0: channel 1 generates 27mhz video dat a 1: channel 1 g enerates 36mhz video dat a [6] o36m2 r w 0: channel 2 generates 27mhz v ideo dat a 1: channel 2 g enerates 36mhz video dat a [7] o36m3 r w 0: channel 3 generates 27mhz video dat a 1: channel 3 g enerates 36mhz video dat a 6.1.27 channel id01 register C offset 63h(default=10h) bit function type description [3:0] ch0num rw assign channel id number in cv_in0a/cv_in0b video data out p ut [7:4] ch1num rw assign channel id number in cv_in1a/cv_in1b video data out p ut 6.1.28 channel id23 register C offset 64h(default=32h) bit function type description [3:0] ch2num rw assign channel id number in cv_in2a/cv_in2b video data out p ut [7:4] ch3num rw assign channel id number in cv_in3a/cv_in3b video data out p ut 6.1.29 pixel output bus tri-state control re gister C offset 65h(default=00h) bit function type description [0] pixout_0 oeb rw pixout_0 [7:0] output tri-state control. 0: put the bus in tri-state mode. 1: put the bus in out p ut mode [1] pixout_1 oeb rw pixout_1 [7:0] output tri-state control. 0: put the bus in tri-state mode. 1: put the bus in out p ut mode [2] pixout_2 oeb rw pixout_2 [7:0] output tri-state control. 0: put the bus in tri-state mode. 1: put the bus in out p ut mode [3] pixout_3 oeb rw pixout_3 [7:0] output tri-state control. 0: put the bus in tri-state mode. 1: put the bus in out p ut mode [7:4] reserved r reset to 0h 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 26? www.pericom.com ????? ? 6.1.30 reserved register C offset 66-6fh 6.1.31 audio clock control register C offset 70h(default=08h) bit function type description [2:0] afmd rw 0: 8khz 1: 16khz 2: 32khz 3: 44.1khz 4: 48khz [3] reserved r reset to 1b [5:4] reserved r reset to 0b [6] s2i_8bit r w 0:sclk_p/lrck_p/sdout_p pin input 16-bit control 1: sclk_p/lrck_p/sdout_p pin input 8-bit control [7] reserved r reset to 0b 6.1.32 i2s audio input control regist er C offset 71h(default=00h) bit function type description [1:0] reserved r reset to 00b [2] sdinpdly rw sdin_p input data delay by one sclk_p clock 0:no delay; 1t delay for i2s interface 1:add 1 sclk_p clock delay in sdin_p input.; 0t delay for left- j ustified interface. [7:3] reserved r reset to 00h 6.1.33 reserved register C offset72h-7ah 6.1.34 sdout_m select (r) register C offset 7bh(default=00h) bit function type description [1:0] reserved r reset to 00b [4:0] i2so_rsel rw select r channe l output on sdout_m pin when sdoutm_i2soen=1 0:select record audio channel line_in0_1 1:select record audio channel line_in1_1 2:select record audio channel line_in2_1 3:select record audio channel line_in3_1 4:select record audio channel line_in0_2 5:select record audio channel line_in1_2 6:select record audio channelline_in2_2 7:select record audio channel line_in3_2 8:select record audio channel line_in0_3 9:select record audio channel line_in1_3 a:select record audio channel line_in2_3 b:select record audio channel line_in3_3 c:select record audio channel line_in0_4 d:select record audio channel line_in1_4 e:select record audio channel line_in2_4 f:select record audio channel line_in3_4 10h:select p la y back audio of the master chi p 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 27? www.pericom.com ????? ? bit function type description 11h:reserved 12h:select playback audio of the slave chip 13h:reserved 14h:playback data output and playback data can adjust volume by df[3:0] 15h:select record audio of channel line_in4_1 16h:select record audio of channel line_in4_2 17h:select record audio of channel line_in4_3 18h:select record audio of channel line_in4_4 others:no audio out p ut [7:5] reserved r reset to 0h 6.1.35 sdout_m select (l) register C offset 7ch(default=00h) bit function type description [1:0] reserved r reset to 00b [4:0] i2so_rsel rw select l channe l output on sdout_m pin when sdoutm_i2soen=1: 0:select record audio channel line_in0_1 1:select record audio channel line_in1_2 2:select record audio channel line_in2_3 3:select record audio channel line_in3_4 4:select record audio channel line_in0_1 5:select record audio channel line_in1_2 6:select record audio channel line_in2_3 7:select record audio channel line_in3_4 8:select record audio channel line_in0_1 9:select record audio channel line_in1_2 a:select record audio channel line_in2_3 b:select record audio channel line_in3_4 c:select record audio channel line_in0_1 d:select record audio channelline_in1_2 e:select record audio channel line_in2_3 f:select record audio channel line_in3_4 10h:select playback audio of the master chip 11h:reserved 12h:select playback audio of the slave chip 13h:reserved 14h:playback data output and playback data can adjust volume by df[3:0] 15h:select record audio of channel line_in4_1 16h:select record audio of channel line_in4_2 17h:select record audio of channel line_in4_3 18h:select record audio of channel line_in4_4 others:no audio out p ut [7:5] reserved r reset to 000b 6.1.36 extended line select register C offset 7dh(default=e4h) bit function type description 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 28? www.pericom.com ????? ? bit function type description [1:0] select output data in data51 position rw 0: line_in4 _ 1 1: line_in4_2 2: line_in4_3 3: line_in4 _ 4 [3:2] select output data in data52 position rw 0: line_in4 _ 1 1: line_in4_2 2: line_in4_3 3: line_in4 _ 4 [5:4] select output data in data53 position r w 0: line_in4 _ 1 1: line_in4_2 2: line_in4_3 3: line_in4 _ 4 [7:6] select output data in data54 position rw 0: line_in4 _ 1 1: line_in4_2 2: line_in4_3 3: line_in4_4 note: if i2s mode is set: l data: dat0-dat1-dat2-dat3-dat4-dat5-dat6-dat7-dat51-dat52 rdata: dat8-dat9-data-datb-datc-datd-date-datf-dat53- dat54 if dsp mode is set: dat0-dat1-dat2-dat3-dat4-dat5-dat6-dat7-dat8-dat9-data- datb-datc-datd-date-datf- dat51-dat52-dat53-dat54 6.1.37 sdout_m registerC offset 7eh(default=00h) bit function type description [5:0] reserved r reset to 00b [6] sdout_m i2s oen r/w define sdout_m pin output 2 word dat a to make standard i2s output 0: mixing data or playback input data are only output on sdout_m 1:l/r data on sdout_m p in is selected b y 0x7b and 0x7c [7] a5outoff r /w 0:line_in4_1/line_in4_2/line_in4_3 /line_in4_4 output on sdout_r 1:line_in4_1/line_in4_2/line_in4_3 /line_in4_4 not out p ut on sdout_ r 6.1.38 mix ratio value for line_in4 regi ster C offset 7fh(default=08h) bit function type description [3:0] mix_ratio4 rw line_in4 ratio value for audio mixing function 0 : 0.39% 1 : 0.78% 2 : 1.56% 3 : 3.12% 4 : 6.25% 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 29? www.pericom.com ????? ? 5 : 12.5% 6 : 25% 7 : 50% other : 100% [7:4] reserved r reset to 00b 6.1.39 software reset registerC offset 80h(default=00h) bit function type description [0] adec0rst w writing one reset the video decoder 0 to its default state but all re g istercontent remain unchan g ed. this bit is sel f -resettin g [1] adec1rst w writing one reset the video decoder 1 to its default state but all register content remain unchanged. this bit is self- resettin g [2] adec2rst w writing one reset the video decoder 2 to its default state but all register content remain unchanged. this bit is self- resettin g [3] adec3rst w writing one reset the video decoder 3 to its default state but all register content remain unchanged. this bit is self- resettin g [4] reserved r r eset to 00b [5] audiorst w writing one reset the audio portion to its default state but all re g ister content remain unchan g ed. this bit is sel f -resettin g [7:6] reserved r reset to 00b 6.1.40 reserved register C offset 81h-84h 6.1.41 video source selection register C offset 85h (default=00h) bit function type description [0] cv_ina0/cv_inb0 selection rw 0: cv_ina0 1: cv_inb0 [1] cv_ina1/cv_inb1 selection rw 0: cv_ina1 1: cv_inb1 [2] cv_ina2/cv_in_b2 selection rw 0: cv_ina2 1: cv_inb2 [3] cv_ina3/cv_inb3 selection rw 0: cv_ina3 1: cv_inb3 [7:4] reserved r reset to 0h 6.1.42 reserved register C offset 86h-88h 6.1.43 audio fs mode registerC offset 89h(default=00h) bit function type description [1:0] reserved r reset to 00b [2] audio fs mode select rw 0: 256fs 1: 320fs [7:3] reserved r reset to 00h 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 30? www.pericom.com ????? ? 6.1.44 reserved register C offset 8ah-9eh 6.1.45 pixclk 0 delay registerC offset 9fh(default=00h) bit function type description [3:0] control clock delay of pixclk_p0 pin rw 0h/1h/3h/7h/fh values are effective 0h: no clock delay 1h: about 2ns more delay, 3h: about 4ns more delay, 7h: about 6ns more delay, fh: about 7ns more dela y [7:4] control clock delay of pixclk_n0 pin rw 0h/1h/3h/7h/fh v alues are effective. 0h: no clock delay 1h: about 2ns more delay, 3h: about 4ns more delay, 7h: about 6ns more delay, fh: about 7ns more dela y 6.1.46 reserved register C offset a0h-b0h 6.1.47 ch8iden register C offset b1h(default=00h) bit function type description [6:0] reserved r reset to 00b [7] ch8iden r /w video channel id number for 8 channels when fast switching is enabled. 0: 4-channel id only. please refer to channel id01 and id34 registers for defining 4 channels id numbers. 1: 8-channel id. the id for each channel is defined as follows. cv_in0a: {1b0, ch0num[2:0]} cv_in1a: {1b0, ch1num[2:0]} cv_in2a: {1b0, ch2num[2:0]} cv_in3a: {1b0, ch3num[2:0]} cv_in0b: {1b1, ch0num[2:0]} cv_in1b: {1b1, ch1num[2:0]} cv_in2b: {1b1, ch2num[2:0]} cv_in3b: {1b1, ch3num[2:0]} 6.1.48 reserved register C offset b2h-c7h 6.1.49 gpio_0_1 mode registerC offset c8h(default=00h) bit function type description [2:0] output mode for gpio_0pin r w select output mode f or gpio_0 pin 0: output hsync 1: output vsync 2: field 3: h-active 4: vh-active 5: 27mhz clock output 6: vh-sync 7: gpp_va1 [3] general pur p ose value rw set g eneral p ur p ose v alue in gpio_0 p in 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 31? www.pericom.com ????? ? bit function type description in gpio_0 pin [6:4] output mode for gpio_1 pin rw select output mode f or gpio_1 pin 0: output hsync 1: output vsync 2: field 3: h-active 4: vh-active 5: 27mhz clock output 6: vh-sync 7: gpp_va2 [7] general purpose value in gpio_1 pin rw set g eneral purpose v alue in gpio_1 pin 6.1.50 gpio_2_3 mode registerC offset c9h(default=00h) bit function type description [2:0] output mode for gpio_2 pin r w select output mode f or gpio_2 pin 0: output hsync 1: output vsync 2: field 3: h-active 4: vh-active 5: 27mhz clock output 6: vh-sync 7: gpp_va1 [3] general purpose value in gpio_2 pin rw set g eneral purpose v alue in gpio_2 pin [6:4] output mode for gpio_3 pin rw select output mode f or gpio_3 pin 0: output hsync 1: output vsync 2: field 3: h-active 4: vh-active 5: 27mhz clock output 6: vh-sync 7: gpp_va2 [7] general purpose value in gpio_3 pin rw set g eneral purpose v alue in gpio_3 pin 6.1.51 video output mode register C offset cah(default=00h) bit function type description [1:0] pixout_0 pin output mode r w0:single output 1: dual channel video output 2:quad channel video output 3: reserved [3:2] pixout_1 pin output mode rw 0: single output 1: dual channel video output 2:quad channel video output 3: reserved 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 32? www.pericom.com ????? ? bit function type description [5:4] pixout_2 pin output mode r w0:single output 1: dual channel video output 2:quad channel video output 3: reserved [7:6] pixout_3 pin output mode rw 0: single output 1: dual channel video output 2:quad channel video output 3: reserved 6.1.52 gpio polarity register C offset cbh (default=00h) bit function type description [3:0] reserved r reset to 0h [4] select gpio_0 pin out p ut polarit y . rw 0: normal 1: inverse p olarit y [5] select gpio_1 pin out p ut polarit y . rw 0: normal 1: inverse p olarit y [6] select gpio_2 pin out p ut polarit y . rw 0: normal 1: inverse p olarit y [7] select gpio_3 pin out p ut polarit y . rw 0: normal 1: inverse p olarit y 6.1.53 pixout output ch2 select register C offset cch (default=39h) bit function type description [1:0] ch2 data selection in pixout_0 rw 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 00b [3:2] ch2 data selection in pixout_1 r w 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 01b [5:4] ch2 data selection in pixout_2 rw 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 10b [7:6] ch2 data selection in pixout_3 r w 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 11b 6.1.54 pixout output ch1 select register C offset cdh (default=e4h) bit function type description 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 33? www.pericom.com ????? ? bit function type description [1:0] ch1 data selection in pixout_0 rw 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 00b [3:2] ch1 data selection in pixout_1 r w 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 01b [5:4] ch1 data selection in pixout_2 rw 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 10b [7:6] ch1 data selection in pixout_3 r w 0: cv_in0 video decoder data 1: cv_in1 video decoder data 2: cv_in2 video decoder data 3: cv_in3 video decoder data reset to 11b 6.1.55 reserved registerC offset ceh 6.1.56 serial mode control regist erC offset cfh(default=00h) bit function type description [6:0] reserved r reset to 00h [7] smd rw cascade audio serial mode. 0: sd_linko is tri stated 1: sd_linko is enabled 6.1.57 reserved registerC offset d0h-d1h 6.1.58 sdout_rm output registerC offset d2h(default=03h) bit function type description [1:0] 16 audios recorded on the sdout_ r pin r reset to 11b [3:2] r_sdoutm rw select the output mode for sdout_m pin 0:the output is controlled by sdoutm_i2soe 1: record audio in sdout_r format 2: record audio in sdout_m format [5:4] reserved r reset to 00b [6] rm_sync rw record and mixing audio data format 0: i2s mode 1: dsp mode [7] data position rw i2s mode 0: mix data on position 0, playback data on position 8 1: mix data on position 8, playback data on position 0 dsp mode 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 34? www.pericom.com ????? ? 0: mix data on position 0, playback data on position 1 1: mix data on position 1, playback data on position 0 6.1.59 sdout_r_seq_1_0 registerC offset d3h(default=10h) bit function type description [3:0] r_seq0 r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seq1 rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 6.1.60 sdout_r_seq_3_2 registerC offset d4h(default=32h) bit function type description [3:0] r_seq2 r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0 _ 2 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 35? www.pericom.com ????? ? 5: line_in1 _ 2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seq3 rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 6.1.61 sdout_r_seq_5_4 registerC offset d5h(default=54h) bit function type description [3:0] r_seq4 r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seq5 rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1 _ 1 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 36? www.pericom.com ????? ? bit function type description 2: line_in2 _ 1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 6.1.62 sdout_r_seq_7_6registerC offsetd6h(default=76h) bit function type description [3:0] r_seq6 r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seq7 rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2 _ 4 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 37? www.pericom.com ????? ? f: line_in3 _ 4 6.1.63 sdout_r_seq_9_8 registerC offset d7h(default=98h) bit function type description [3:0] r_seq8 r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seq9 rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 6.1.64 sdout_r_seq_b_a registerC offset d8h(default= bah) bit function type description [3:0] r_seqa r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2 _ 2 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 38? www.pericom.com ????? ? 7: line_in3 _ 2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seqb rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 6.1.65 sdout_r_seq_d_c registerC offset d9h(default= dch) bit function type description [3:0] r_seqc r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seqd rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3 _ 1 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 39? www.pericom.com ????? ? 4: line_in0 _ 2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 6.1.66 sdout_r_seq_f_e registerC offset dah(default= feh) bit function type description [3:0] r_seqe r w the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 [7:4] r_seqf rw the sequence on the sdout_ r 0: line_in0_1 1: line_in1_1 2: line_in2_1 3: line_in3_1 4: line_in0_2 5: line_in1_2 6: line_in2_2 7: line_in3_2 8: line_in0_3 9: line_in1_3 a: line_in2_3 b: line_in3_3 c: line_in0_4 d: line_in1_4 e: line_in2_4 f: line_in3 _ 4 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 40? www.pericom.com ????? ? 6.1.67 i2s master control registerC offset dbh(default= c2h) bit function type description [0] aclkrmaste r r w 0: sclk_r pin is slave mode 1: sclk_r p in is master mode [1] reserved r reset to 1b [2] sdout_rpin data format rw per word unit on sdout_r pin 0: 16bit 1: 8bit [3] pb_sync rw the audio data format for audio playback mode 0: i2s mode for playback 1: dsp mode for p la y back [4] pb_lrsel rw select the audio da ta position in playback input i2s mode: 0: 1st left channel audio data 1: 1st right channel audio data dsp mode: 0: 1st channel audio data 1: 2nd channel audio dat a [5] pb_maste r rw the operation mode for playback mode. 0: sclk_p pin is slave mode 1: sclk_p p in is master mode [7:6] reserved r reset to 11b 6.1.68 mix_mute registerC offset dch(default=00h) bit function type description [4:0] mix_mute r mute function enable 0 : disable 1: mute bit[0] : line_0_1; bit[1] : line_1_1; bit[2] : line_2_1; bit[3] : line_3_1; bit[4] : pla y back audio in p ut; [7:5] reserved r reset to 00b 6.1.69 mix ratio value for line_in0 & line_in1 register C offset ddh (default=88h) bit function type description [3:0] mix_ratio0 rw line_in0 ratio value for audio mixing function 0 : 0.39% 1 : 0.78% 2 : 1.56% 3 : 3.12% 4 : 6.25% 5 : 12.5% 6 : 25% 7 : 50% 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 41? www.pericom.com ????? ? other : 100% [7:4] mix_ratio1 r /w line_in1 ratio value for audio mixing function 0 : 0.39% 1 : 0.78% 2 : 1.56% 3 : 3.12% 4 : 6.25% 5 : 12.5% 6 : 25% 7 : 50% other : 100% 6.1.70 mix ratio value for line_in2 & line_in3 register C offset deh (default=88h) bit function type description [3:0] mix_ratio2 rw line_in2 ratio value for audio mixing function 0 : 0.39% 1 : 0.78% 2 : 1.56% 3 : 3.12% 4 : 6.25% 5 : 12.5% 6 : 25% 7 : 50% other : 100% [7:4] mix_ratio3 r /w line_in3 ratio value for audio mixing function 0 : 0.39% 1 : 0.78% 2 : 1.56% 3 : 3.12% 4 : 6.25% 5 : 12.5% 6 : 25% 7 : 50% other : 100% 6.1.71 pb ratio register C offset dfh (default=08h) bit function type description [3:0] ratio value for audio mixing rw playback input ratio value for audio mixing function 0 : 0.39% 1 : 0.78% 2 : 1.56% 3 : 3.12% 4 : 6.25% 5 : 12.5% 6 : 25% 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 42? www.pericom.com ????? ? 7 : 50% other : 100% [7:4] reserved r reset to 0h 6.1.72 mixing output control regist erC offset e0h(default=14h) bit function type description [4:0] mix_outsel r w define the final audio output for analog and digital mixing out: 0h: line_in0_1 1h: line_in1_1 2h: line_in2_1 3h: line_in3_1 4h: line_in0_2 5h: line_in1_2 6h: line_in2_2 7h: line_in3_2 8h: line_in0_3 9h: line_in1_3 ah: line_in2_3 bh: line_in3_3 ch: line_in0_4 dh: line_in1_4 eh: line_in2_4 fh: line_in3_4 10h: playback audio of the master chip 11h: reserved 12h: playback audio of the slave chip 13h: reserved 14h: playback data output and playback data can adjust volume by dfh[3:0] 15h: line_in4_1 16h line_in4_2 17h: line_in4_3 18h: line_in4_4 others: no audio output [7:5] reserved r reset to 000b 6.1.73 reserved registerC offset e1h-f8h 6.1.74 pixclk output mode registerC offset f9h (default=00h) bit function type description [0] pi x clk _ pf rw output frequency mode of pixclk_po pin. 0: output one of 27mhz, 54mhz or 180mhz frequency. 1: out p ut one of 36mhz, 72mhz or 144mhz fre q uenc y . [1] pi x clk _ nf r w output frequency mode of pixclk_no pin. 0: output one of 27mhz, 54mhz or 180mhz frequency. 1: out p ut one of 36mhz, 72mhz or 144mhz fre q uenc y . [7:2] reserved r reset to 0h 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 43? www.pericom.com ????? ? 6.1.75 ccir656 control registerC offset fah(default=00h) bit function type description [1:0] pi x out format control w control the data frequency of pi x out pins 0: 27m/36mhz data output 1: 54m/72mhz data output 2: 108m/144mhz data output reset to 00b [3:2] reserved w reset to 00b [4] reserved r reset to 0b [5] reserved r reset to 0b [6] ccir656 output enable rw 0: all outputs are tri-stated 1:all outputs(pixout_n/pix clk_po/pixclk_no) are enabled [7] reserved r reset to 0b 6.1.76 clock polarity registerC offset fbh(default=0fh) bit function type description [1:0] vdet_mode rw define the polarity of state register and interrupt request for video detection. 0: no interrupt request by the video detection 1: make the interrupt request rising only when the video comes in 2: make the interrupt request falling only when the video goes out 3: make the interrupt request rising and falling whenthe video comes in and goes out [3:2] adet_mode rw define the polarity of state register and interrupt request for audio detection. 0: no interrupt request by the audio detection 1: make the interrupt request rising only when the audio comes in 2: make the interrupt request falling only when the audio goes out 3: make the interrupt request rising and falling whenthe audio comes in and g oes out [4] irqpol rw select the polarity of interrupt request through theirq pin. 0: falling edge requests the interrupt and keeps itsstate until cleared 1: rising edge requests the interrupt and keeps itsstate until cleared [5] irqena r/w rw enable/disable the interrupt request through the irq pin 0: disable 1: enable [6] pixclk_p_pol rw 0:the p olarit y of pixclk_pis not inversed 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 44? www.pericom.com ????? ? 1: the p olarit y of pixclk_p is inversed [7] pixclk_n_pol rw 0:the polarity of pixclk_n is not inversed 1: the p olarit y of pixclk_n is inversed 6.1.77 video/audio detection enable registerCoffset fch (default=ffh) bit function type description [7:0] avdet_en r w enable the status register updated and interrupt request if the following video or audio source is detected. the mapping of video/audio input to each bit of the register is defined as below. bit0: video input cv_in0. bit1: video input cv_in1. bit2: video input cv_in2. bit3: video input cv_in3. bit4: audio input line_in0. bit5: audio input line_in1. bit6: audio input line_in2. bit7: audio input line_in3. 0: disable status register updated and interrupt request 1: enable status re g ister u p dated and interru p t re q uest 6.1.78 video/audio detection status re gisterCoffset fdh (default=00h) bit function type description [7:0] avdet_status r display the detection status of each video or audio source according to avdet_en, vdet_mode and adet_mode. the mapping of video/audio input to each bit of the register is defined as below. the bits will be cleared once the register is read by software except vdet_mode =3 or adet_mode=3. bit0: video input cv_in0. bit1: video input cv_in1. bit2: video input cv_in2. bit3: video input cv_in3. bit4: audio input line_in0. bit5: audio input line_in1. bit6: audio input line_in2. bit7: audio input line_in3. 0: inactive. no event detected after the last access to this bit. 1: active. an event is detected. 6.1.79 device id_h registerC offset feh(default=00h) bit function type description [5:0] reserved r reset to 00h 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 45? www.pericom.com ????? ? [7:6] dev_id[6:5] r reset to 00b 6.1.80 device id - l registerC offset ffh(default=e8h) bit function type description [2:0] rev_id r reset to 000b [7:3] dev_id[4:0] r reset to 1dh 7 electrical characteristics 7.1 absolute maximum ratings (above which useful life may be impa ired. for user guidelines, not tested.) parameters value note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. supply voltage range 3.3v power supply -0.3v to 4.5v core power 1.0v supply -0.3v to 1.8v t a operating free-air temperature range -45 c to 85 c t stg storage temperature -65 c to 150 c 7.2 operating conditions s y mbol parameters min. t y p. max. unit vd33,adc_vdd, adac_vdd, vddpll 3.3v power supply voltage 3.0 3.3 3.6 v vddc core power su pp l y volta g e 0.9 1.0 1.1 v v i(p-p) analo g in p ut volta g e (ac-cou p lin g necessar y ) 0 1.6 v t a ambient free-air tem p erature 0 70 c 7.3 dc electrical characteristics s y mbo l parameters conditions min. t y p. max. unit v ih di g ital in p ut hi g h volta g e 2.0 3.6 v v il di g ital in p ut low volta g e -0.3 0.8 v v oh di g ital out p ut hi g h volta g e 2.4 v 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 46? www.pericom.com ????? ? v ol di g ital out p ut low volta g e 0.4 v i l in p ut leaka g e current +/- 1 ua i oz tri-state out p ut leaka g e current +/- 1 ua i oh hi g h level out p ut current v oh =2.4v 11 17 24 ma i ol low level out p ut current v ol =0.4v 8 13 16 ma r p u in p ut p ull-u p resistance vin=0 61 75 105 k r p d in p ut p ull-down resistance vin=dvdd33 101 199 330 k t j junction tem p erature -40 25 125 c 7.3.1 power dissipation s y mbol parameters test condition min. t y p. max. unit 3.3v total total 3.3v power volta g e connect all video/audio pins 218 ma 1.0v total core supply voltage (vddc) connect all video/audio pins 158 ma p tot total power consum p tion connect all video/audio pins 741 mw 7.3.2 power-on sequence of 3.3v and 1.0v power s y mbol parameters min t y p ma x unit t1 interval dela y between io and core power su pp l y 0 10 500 ms 7.3.3 crystal specifications parameters min t y p ma x unit fre q uenc y 27 mhz fre q uenc y tolerance 50 pp m 7.4 ac electrical characteristics s y mbol paramete r test condition min t y p ma x unit zi in p ut im p edance analo g video in p uts b y desi g n4 0 k ci in p ut ca p acitance analo g video in p uts b y desi g n1 0 p f dnl differential non linearit y 2 lsb inl inte g ral non linearit y 3 lsb vi full scale input range the expected full input range is only 0.5 v pp to 1.0 v pp . 0.25 1.6 vpp sn r si g nal to noise ratio this is measured with a -1db full scale input signal and adjusted for full scale am p litude 50 db thd total harmonic distortion -50 db analo g in p ut bandwidth this bandwidth does not include 300 mhz 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 47? www.pericom.com ????? ? limitations due to the source impedance of 37.5 and loading on the board, 30 p f (140 mhz). 7.4.1 audio electrical characteristics s y mbo l paramete r test condition min t y p ma x unit zi in p ut im p edance analo g video in p uts b y desi g n 40 k ci in p ut ca p acitance analo g v ideo in p uts b y desi g n 10 p f vi maximum in p ut ran g e 0.25 1.6 v sn r si g nal to noise ratio 85 db dn r d y namic ran g e 80 db thd total harmonic distortion -75 db 7.4.2 pixel clock and video data timing symbol parameter min typ max unit ts1 setup from pixclk_po to pixout (144mhz) 2.6 - 4.3 ns th1 hold from pixclk_po to pixout (144mhz) 2.7 - 4.4 ns ts2 setup from pixclk_po to pixout (108mhz) 3.8 - 5.4 ns th2 hold from pixclk_po to pixout (108mhz) 3.9 - 5.5 ns ts3 setup from pixclk_po to pixout (72mhz) 5.6 - 7.6 ns th3 hold from pixclk_po to pixout (72mhz) 6.3 - 8.3 ns ts4 setup from pixclk_po to pixout (54mhz) 8.2 - 10.3 ns th4 hold from pixclk_po to pixout (54mhz) 8.3 - 10.4 ns ts5 setup from pixclk_po to pixout (36mhz) 14.1 - 16.1 ns th5 hold from pixclk_po to pixout (36mhz) 11.7 - 13.7 ns ts6 setup from pixclk_po to pixout (27mhz) 19 - 20.9 ns th6 hold from pixclk_po to pixout (27mhz) 16.1 18 ns the timing value is measured by the following conditions: (1) the clock delay control on pixclk_po pin is set to zero; (2) the clock polarity control on pixclk_po pin is not inverted. 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 48? www.pericom.com ????? ? figure 7-1 otdm is operated at 144mhz figure 7-3 otbm at 72/36mhz figure 7-4 otbm at 54/27mhz figure 7-2otdm is operated at 108mhz 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 49? www.pericom.com ????? ? 7.4.3 audio interface timing s y mbo l paramete r test condition min t y p ma x unit t s_lrck_ r setu p time for lrck_ r slave mode 0.2 - ns t h_lrck_ r hold time for lrck_ r 0.4 - ns t s_pb setu p time for lrck_p and sdin_p 0.1 - ns t h_pb hold time for lrck_p and sdin_p 0.55 - ns t rm_pd pro p a g ation dela y for sdout_r/m, lrck_ r master mode 2.6 - 5.9 ns t pb_pd propagation delay for lrck_p 2.2 - 4.8 ns figure 7-5 digital serial audio in terface slave mode timing diagram figure 7-6 digital serial audio inte rface master mode timing diagram 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 50? www.pericom.com ????? ? 7.4.5 i2c host port timing s y mbo l paramete r test condition min t y p ma x unit t1 bus free time between stop and start 1.3 s t2 setu p time, (re p eated) start condition 0.6 s t3 hold time, (re p eated) start condition 0.6 s t4 setu p time, stop condition 0.6 ns t5 data setu p time 100 ns t6 data hold time 0 0.9 s t7 rise time, vc1(sda) and vc0(scl) si g nal s p ecified b y desi g n 250 ns t8 fall time, vc1(sda) and vc0(scl) si g nal s p ecified b y desi g n 250 ns c b ca p acitive load for each bus line s p ecified b y desi g n 400 p f f i2c i 2 c clock fre q uenc y 400 khz fi g ure 7-7i2c host port timin g 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 51? www.pericom.com ????? ? 8 packaging mechanical note: for latest package info, please check: http://www.pericom.com/produc ts/packaging/mechanicals.php 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 52? www.pericom.com ????? ? 9 ordering information ordering code package co de package description pi7vd9004abhfd fd128(no epad) 128-lqfp, pb-free & green notes: 1. thermal characteristics can be found on the co mpany web site at www.pericom.com/packaging/ 2. adding e = pb-free, i=industrial, fp=package code, x suffix = tape/reel 10 related product information part numbe r product description pi7vd9008h 8-channel 960h video decoder with 10-bit audio adc pi7vd9004h 4-channel 960h video decoder with 10-bit audio asc PI7C9X9208 8-channel d1 pcie video decoder with 16-bit audio adc pi7c9x9204s 4-channel d1 pcie video decoder with 16-bit audio adc pi7vd9008hevb pi7vd9008 evaluation kit pi7vd9208hevb pi7vd9208 evaluation kit 11 reference document information document description re g ister datasheet pi7vd9004abh re g ister s p ecification a pp lication note reference schematic and board la y out a pp lication notes 13-0174
pi7vd9004abh adaptive eq 4-channel 960h video decoder pericom ? semiconductor ? corporation ?? 53? www.pericom.com ????? ? information in this document is provided in connection with pericom product. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in pericoms terms and conditions of sale for such products including liability or warra nties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. pericom may make changes to specifications and product descri ptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. pericom reserves these for future definition and shall have no responsibility what soever for conflicts or incompat ibilities arising from future changes to them. the products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specification. current charac terized errata are available on request. contact your local pericom sales office or your distributor to obtain the lates t specifications and before placing your product order. copyright 2013 pericom corporation. all rights reserved. pericom and the pericom logo are trademarks of pericom corporation in the u.s. and other countries. 13-0174

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